1. Field of the Invention
The present invention relates to a clock generator in a semiconductor system using semiconductor integrated circuit and semiconductor integrated circuit element, and to a clock generator which enables the high speed operation thereof by decreasing delay between the input clock and output clock.
2. Description of Related Art
FIG. 1 is a block diagram of an example of construction of a conventional clock generator.
In FIG. 1, reference numeral 61 designates a crystal oscillating circuit (CO), 62 a multiplexer, 63 a frequency dividing circuit, 64 a clock driver, 65 an RES# signal synchronizing circuit, and 66 an ADS# signal synchronizing circuit. Moreover, reference numeral 67 designates a quartz resonator connecting terminal, 68 an external clock signal input terminal, 69 a clock (CLK2) signal output terminal, 70 a clock (CLK) signal output terminal, 71 a clock signal source selecting terminal, 72 an RES# signal input terminal, 73 a RESET signal output terminal, 74 an ADS# signal input terminal, and 75 an AD50 signal output terminal.
Next, explanation will be given on an operation of a conventional clock generator of a construction mentioned above.
A quartz resonator having oscillating frequency being equal to clock frequency expected to be outputted from the clock (CLK2) signal output terminal 69 is connected with the quartz resonator connecting terminal 67, and an external clock signal is connected with the external clock signal input terminal 68 respectively as clock signal sources. And in the case where the clock signal source selecting terminal 71 is set at low level, the terminal 68 is selected as clock signal source, and in the case where it is set at high level, the terminal 67 is selected respectively by the multiplexer 62. The clock signal source selected by the multiplexer 62 is outputted therefrom to be inputted to the clock driver 64 and driven from the clock (CLK2) signal output terminal 69.
On the other hand, the clock signal source outputted from the multiplexer 62 is inputted to the frequency dividing circuit 63, and driven from the clock (CLK) signal output terminal 70 after the frequency thereof being divided into two.
In addition, explanation on operations of the RES# signal synchronizing circuit 65 and the ADS# signal synchronizing circuit 66 will be omitted as there is no direct relation with the present invention.
Moreover, as shown in the block diagram in FIG. 1, although a non-overlap clock is widely used in order to prevent malfunctioning due to lacing of data, as a clock for driving the 1/2 frequency dividing circuit usually comprising flip-flop of two stages, the clock and the generating circuit thereof are omitted.
FIG. 2 shows a block diagram showing a construction of a conventional clock generator being provided with the non-overlap clock generating circuit 76.
In the case where the construction of the clock generator is that of the block diagram in FIG. 2, the clock signal source outputted from the multiplexer 62 is inputted to the non-overlap clock generating circuit 76. The non-overlap clock generating circuit 76 generates clock signal 77 of two-phase having non-overlap period from the inputted clock signal source. And the frequency dividing circuit 63 is not directly driven by the output of the multiplexer 62, but is driven by the non-overlap clock 77 generated by the non-overlap clock generating circuit 76.
In addition, other operations are quite the same as those of the clock generator shown in a block diagram in FIG. 1 above-mentioned.
Moreover, as an example of a conventional clock generator, a construction as shown in a block diagram in FIG. 3, for example.
In FIG. 3, reference numeral 1 designates an external clock. The external clock 1 is inputted from a pad 2 to be a first clock C1 through inverters 31 and 32 of two stages of a buffer 3, and to be a second clock C2 directly from the inverter 31, these clocks C1 and C2 respectively being inputted to a non-overlap clock generating circuit 51 of an internal clock logical value generating circuit 5
FIG. 4 is a circuit diagram showing an concrete construction of the non-overlap clock generating circuit 51. Both of the first clock C1 and the second clock C2 having inputted to the non-overlap clock generating circuit 51 are inputted to the frequency dividing circuit 52 as a fourth clock C4 and a third clock C3 through NOR gates and inverters of two stages, respectively.
FIG. 5 is a circuit diagram showing a concrete construction of the frequency dividing circuit 52. The frequency dividing circuit 52 comprises D latches D1 and D2 of two stages. The third clock C3 inputted into the frequency dividing circuit 52 is outputted as sixth clock C6 through one D latch D1 and the fourth clock C4 inputted into the frequency dividing circuit 52 is outputted as a fifth clock C5 through the other D latch D2, respectively.
The fifth clock C5 is outputted as a second internal clock IC2 through an inverter 18 and an internal clock outputting buffer 15'. On the other hand, the sixth clock C6 is outputted as a first internal clock IC1 only through an internal clock outputting buffer 15.
FIG. 6 is a timing chart showing a waveform of above-mentioned each clock.
Compared with the external clock 1 shown in FIG. 6(a), the second clock C2 through the inverter 31 of the buffer 3 is inverted and delayed a little, as shown in FIG. 6(c), and the first clock C1 through inverters 31 and 32 of two stages of the buffer 3 is inverted two times and delayed about two times of the second clock C2, as shown in FIG. 6(b).
The fourth clock C4 shown in FIG. 6(e) is delayed by the time required for the first clock C1 passing through one NOR gate and two inverters from C1, and the third clock C3 shown in FIG. 6(d) is generated in the non-overlap state with the fourth clock C4.
And the sixth clock C6 shown in FIG. 6(g) is generated from the third clock C3 due to delay corresponding to one D latch, and the first internal clock IC1 is generated shown in FIG. 6(h) from the sixth clock C6 due further to delay of time to pass one internal clock output buffer 15.
Accordingly, time delay shown by Td in FIG. 6 is generated between the external clock 1 shown in FIG. 6(a) and the first internal clock IC1 shown in FIG. 6(h) .
In the above-mentioned first conventional clock generator, until the frequency-divided clock is generated from the clock signal source outputted from the multiplexer 62 and is outputted, it is to be through the frequency dividing circuit 63 in the case of the construction example, shown in FIG. 1, or is to be through the frequency dividing circuit 63 and non-overlap clock generating circuit 73 in the case of the construction example shown in FIG. 2, in which the frequency dividing circuit 52 is driven by the non-overlap clock 17. That is to say, the critical pass between the inputted external clock being the source clock signal and the output clock is;
external clock.fwdarw. PA1 non-overlap signal generating circuit 51.fwdarw. PA1 frequency dividing circuit 52.fwdarw. PA1 clock driver 15. PA1 (1) in the case where input to the CK input terminal PA1 (2) in the case where input to the CK input terminal PA1 (3) in the case where input to the CK input terminal PA1 (4) in the case where input to the CK input terminal PA1 (1) in the case where input to the C input terminal 802 is "1". PA1 (2) in the case where input to the C input terminal. 802 PA1 input clock.fwdarw. PA1 latch means.fwdarw. PA1 clock driver, PA1 which is shorter than that of a conventional clock generator, and moreover the time delay thereof is largely reduced as a non-overlap clock generating circuit whose delay is especially large is not integrated in the critical pass.
Especially, as the non-overlap clock generating circuit 51 is composed generally of a chain of gates, the delay thereof is made large as a necessary consequence. Accordingly, there is a problem that the time delay between input clock (external clock) and output clock is made large.
In addition, also when the second conventional clock generator is used, a large time delay shown by Td in FIG. 6 is generated.
Next, explanation will be given on Japanese Patent Application Laid-Open No. 1-276327 (1989) as a third conventional example of a clock generator referring to drawings thereof.
FIG. 7 is a block diagram showing a construction of a clock generator disclosed in aforementioned Japanese Patent Application Laid-Open No. 1-276327 (1989).
In FIG. 7, reference numeral 101 designates an input terminal of a reference clock, 102 a D flip-flop functioning as a 1/2 frequency divider, 103 a D flip-flop, 104 a set/reset flip-flop, and 105 designates a D latch.
Numerals 109 and 110 designate clock output terminals and respectively output 1/2 frequency-divided clock and 1 frequency-divided clock of reference clocks inputted to the clock input terminal 101. A reference numeral 106 designates an input buffer, and 107, 108 designate output buffers.
The reference clock inputted from the clock input terminal 101 is given to clock input CK of the D flip-flop 102 and to D input of the D latch 105 through the input buffer 106.
Q output of the D flip-flop 102 is connected to D input of the D flip-flop 102 itself and Q output to D input of the D flip-flop 103, and Q output of the D flip-flop 103 is outputted to the output terminal 109 through the output buffer 107.
Q output and Q output of the D latch 105 are respectively outputted to S input and R input of the set/reset flip-flop 104. And Q output of the set/reset flip-flop 104 is outputted to the output terminal 110 through the output buffer 108.
By the way, explanation will be given in the following on the D flip-flops 102 and 103 used in a clock generator of such a construction as above-mentioned, referring to a circuit diagram of FIG. 8 showing circuit construction of the D flip-flops 102 and 103.
In FIG. 8, reference numeral 901 designates a D input terminal inputting data, 902 a CK terminal inputting clock, 903 and 904 a Q output terminal and Q output terminal respectively, and 905 and 906 inverters, 907 an NAND gate, 908 through 910 OR-NAND gates respectively in each of which an OR gate and an NAND gate are integrated.
Here, logical relation among the D input terminal 901, CK input terminal 902, Q output terminal 903, and Q output terminal 904 is a so called rising edge trigger D flip-flop, and expressed in relation shown in Table 1.
TABLE 1 ______________________________________ D CK Q .sup.-- Q ______________________________________ 1 0 .fwdarw. 1 1 0 0 0 .fwdarw. 1 0 1 X OTHER THAN ABOVE Q .sup.-- Q ______________________________________
In addition, the D flip-flops 102 and 103 shown in FIG. 7 is respectively so constructed that the OR-NAND gate 908 and the inverter 906 shown in FIG. 8 may function as a set/reset flip-flop of input stage, and the OR-NAnd gates 909 and 910 may function as a set/reset flip-flop of output stage. The operation of the D flip-flops 102 and 103 of a construction shown in FIG. 8 is as follows.
902 is "0".
As output of the inverter 905 is "1", OR input of the OR-NAND gates 909 and 910 in the set/reset flip-flop of output stage is "1", and there is no new input, the output state in the past will be maintained. Accordingly, values of Q output terminal 903 and Q output terminal 904 do not change. In the set/reset flip-flop of input stage, as the NAND gate 907 turns into ON state, the state of the D input terminal 901 is taken in the OR-NAND gate 908 and the reversed value thereof becomes output of the inverter 906. But one OR input of the OR-NAND gate 908 is in "1" state of the inverter 905, the set/reset flip-flop of input stage is not in a holding state.
902 changes from "0" to "1".
The output of the inverter 905 changes from "1" to "0". Therefore, the NAND gate 907 changes from ON state to OFF state and the set/reset flip-flop of input stage takes in the state of the D input terminal 901 being immediately before the change to the OR-NAND gate 908, and the NAND gate 907 shifts to a holding state. On the other hand, in the set/reset flip-flop of output stage, as OR inputs of the OR-NAND gates 909 and 910 change from "1" to "0", the state of the set/reset flip-flop of input stage are taken in to be outputted to the Q output terminal 903 and Q output terminal 904.
902 is "1".
As the NAND gate 907 becomes OFF state, new data is not taken in.
902 changes from "1" to "0".
The NAND gate 907 changes from OFF state to ON state, thereby OR inputs of the NAND gates 909 and 910 become "1"according to the inverter 905 much faster than the information of the D input terminal 901 is transmitted to these gates. Accordingly, the set/reset flip-flop of output stage becomes a holding state, and outputs from the Q output terminal 903 and Q output terminal 904 do not change.
Next, explanation will be given on the D latch 105 referring to a circuit diagram in FIG. 9 showing it circuit construction. In FIG. 9, reference numeral 801 designates a D input terminal inputting data, 802 a C input terminal inputting enable signal, 803 and 804 a Q output terminal and Q output terminal respectively outputting data, 805 and 806 OR-NAND gates, and 807 designates an inverter.
Here, logical relation among the D input terminal 801, C input terminal 802, Q output terminal 803, and Q output terminal 804 is the one as expressed in Table 2.
TABLE 2 ______________________________________ D C Q .sup.-- Q ______________________________________ 1 1 1 0 0 1 0 1 X 0 Q .sup.-- Q ______________________________________
The operation of the D latch 105 of such a construction as shown in FIG. 9 is as follows.
As OR outputs of the OR-NAND gates 805 and 806 are both "1", the information of the D input terminal 801 is transmitted to the Q output terminal 803 through the OR-NAND gates 800 and 806. To the Q output terminal 804, the reversed value of the Q output terminal 803 is transmitted through the inverter 807.
is "0".
A set/reset flip-flop is constructed by the OR-NAND gate 806 and the inverter 807. In the case where the Q output terminal 803 holds "0", as OR input of the OR-NAND gate 805 is "0", the gate 805 becomes OFF state and the information of the D input terminal 801 is not taken in. And in the case where the Q output terminal 803 holds "1", as 0R input of the OR-NAND gate 806 is "0", the information from the OR-NAND gate 805 is not taken in. In either case, regardless of the information of the D input terminal 801, the information before the C input terminal 802 changes its value from "1" to "0" is held at the Q output terminal 803 and the Q output terminal 804.
Next, explanation will be given on the set/reset flip-flop 104, referring to a circuit diagram of FIG. 10 showing is circuit construction.
In FIG. 10, reference numeral 701 designates an S input terminal, 702 an R input terminal, 703 a Q output terminal, 704 a Q output terminal, and 705 and 706 designates NOR gates.
Here, as the S input terminal 701 and the R input terminal 702 are connected directly with the Q output terminal 704 and Q output terminal 703 of the D latch respectively, when one input is "1", the other is "0".
Logical relation among the S input terminal 701, R input terminal 702, Q output terminal 704, and Q output terminal 703 is such as expressed in Table 3 according to the NOR gates 705 and 706.
TABLE 3 ______________________________________ S R Q .sup.-- Q ______________________________________ 1 0 1 0 0 1 0 1 ______________________________________
In the following, explanation will be given on the operation of the third conventional clock generator shown in the block diagram of FIG. 7, referring to a timing chart of FIG. 11.
A waveform shown in FIG. 11(a) is the one of reference clock inputted to the clock input terminal 101, and such a clock is taken in a clock generator constructed on an LSI through the input buffer 106 to be inputted to the CK input terminal of the D flip-flop 102.
In the D flip-flop 102, as Q output is connected to D input thereof, every time the waveform shown in FIG. 11(a) changes from "0" to "1", data of reverse polarity to the past is outputted as Q output. This waveform is shown in FIG. 11(b). That is, the D flip-flop 102 functions as a 1/2 frequency divider.
The Q output terminal of the D flip-flop 102 is given to the CK input of the D flip-flop 103. The output waveform after the output of the D flip-flop 103 passed-through the output buffer 107, that is, 1/2 frequency-divided clock 109 is shown in FIG. 11(c).
On the other hand, the buffered reference clock by the input buffer 106 is also inputted to D input of the D latch 105. However, as C input of the D latch 105 is fixed to be "1", the Q output thereof becomes to be same waveform (although delayed) as the reference clock as shown in FIG. 11(d).
The waveform shown in FIG. 11(e) is the output waveform of the set/reset flip-flop 104 after passing the output buffer 108. As the set/reset flip-flop 104 is directly connected with the output of the D latch 105, the D input terminal of the D latch 105 is connected with the clock input terminal 101 through the input buffer 106, and the C input terminal of the D latch 105 is fixed to be "1", a waveform shown in FIG. 11(e) is the one of the reference clock shown in FIG. 11(a) being delayed.
By the way, in the aforementioned third conventional clock generator disclosed in Japanese Patent Application Laid-Open No. 1-276327 (1989), although phases of the generated clocks match with each other, the number of gates from the input terminal of the reference clock to the output terminal of the generated clock is large. Therefore, the delay generated clock is large as compared with the reference clock. For example, in the case where internal clock is generated, if a phase difference between external clock (reference clock) and itself is large, a sampling of external signal cannot be performed as desired, leading to much possibility of malfunction.
In addition, the D flip-flop itself has many gates, leading to a problem that a layout area on an LSI becomes large.